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PX1011B
PCI Express stand-alone X1 PHY
Rev. 02 -- 19 March 2008 Product data sheet
1. General description
The PX1011B is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The PX1011B PCI Express PHY is compliant to the PCI Express Base Specification, Rev. 1.0a, and Rev. 1.1. The PX1011B includes features such as Clock and Data Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection, and provides superior performance to the Media Access Control (MAC) layer devices. The PX1011B is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface. Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE) specification, enhanced and adapted for off-chip applications with the introduction of a source synchronous clock for transmit and receive data. The 8-bit data interface operates at 250 MHz with SSTL_2 signaling. The SSTL_2 signaling is compatible with the I/O interfaces available in FPGA products. The PX1011B PCI Express PHY supports advanced power management functions. The PX1011BI is for the industrial temperature range (-40 C to +85 C).
2. Features
2.1 PCI Express interface
I I I I I I I I I I Compliant to PCI Express Base Specification 1.1 Single PCI Express 2.5 Gbit/s lane Data and clock recovery from serial stream Serializer and De-serializer (SerDes) Receiver detection 8b/10b coding and decoding, elastic buffer and word alignment Supports loopback Supports direct disparity control for use in transmitting compliance pattern Supports lane polarity inversion Low jitter and Bit Error Rate (BER)
2.2 PHY/MAC interface
I I I I Based on Intel PHY Interface for PCI Express architecture v1.0 (PIPE) Adapted for off-chip with additional synchronous clock signals (PXPIPE) 8-bit parallel data interface for transmit and receive at 250 MHz 2.5 V SSTL_2 class I signaling
NXP Semiconductors
PX1011B
PCI Express stand-alone X1 PHY
2.3 JTAG interface
I JTAG (IEEE 1149.1) boundary scan interface I Built-In Self Test (BIST) controller tests SerDes and I/O blocks at speed I 3.3 V CMOS signaling
2.4 Power management
I Dissipates < 300 mW in L0 normal mode I Support power management of L0, L0s and L1
2.5 Clock
I 100 MHz external reference clock with 300 ppm tolerance I Supports spread spectrum clock to reduce EMI I On-chip reference clock termination
2.6 Miscellaneous
I LFBGA81 lead-free package I Operating ambient temperature N Commercial: 0 C to +70 C N Industrial: -40 C to +85 C I ESD protection voltage for Human Body Model (HBM): 2000 V
3. Quick reference data
Table 1. VDDD1 VDDD2 VDDD3 VDD VDDA1 VDDA2 fclk(ref) Tamb Quick reference data Conditions for JTAG I/O for SSTL_2 I/O for core for high-speed serial I/O and PVT for serializer for serializer operating commercial industrial 0 -40 +70 +85 C C Min 3.0 2.3 1.15 1.15 1.15 3.0 99.97 Typ 3.3 2.5 1.2 1.2 1.2 3.3 100 Max 3.6 2.7 1.3 1.3 1.3 3.6 100.03 Unit V V V V V V MHz digital supply voltage 1 digital supply voltage 2 digital supply voltage 3 supply voltage analog supply voltage 1 analog supply voltage 2 reference clock frequency ambient temperature Symbol Parameter
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PX1011B
PCI Express stand-alone X1 PHY
4. Ordering information
Table 2. Ordering information Solder process Pb-free (SnAgCu solder ball compound) Package Name PX1011B-EL1/G LFBGA81 LFBGA81 Description plastic low profile fine-pitch ball grid array package; 81 balls; body 9 x 9 x 1.05 mm plastic low profile fine-pitch ball grid array package; 81 balls; body 9 x 9 x 1.05 mm Version SOT643-1 SOT643-1 Type number
PX1011BI-EL1/G Pb-free (SnAgCu solder ball compound)
5. Marking
Table 3. Line A B C Lead-free package marking Marking PX1011B-EL1/G PX1011BI-EL1/G[1] xxxxxxx 2PGyyww diffusion lot number manufacturing code: 2 = diffusion site P = assembly site G = lead-free yy = year code ww = week code
[1] Industrial temperature range.
Description full basic type number
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PX1011B
PCI Express stand-alone X1 PHY
6. Block diagram
PCI Express MAC
TXCLK
TXDATA [7:0]
RXCLK
RXDATA [7:0]
RESET_N
PCI Express PHY
Ln_TxData0
REGISTER 8
Ln_TxData1 8b/10b ENCODE PARALLEL TO SERIAL
10b/8b DECODE
ELASTIC BUFFER 10 SERIAL TO PARALLEL K28.5 DETECTION
250 MHz clock
DATA RECOVERY CIRCUIT CLK GENERATOR
CLOCK RECOVERY CIRCUIT PLL
TX I/O
REFCLK I/O
RX I/O
bit stream at 2.5 Gbit/s
TX_P TX_N REFCLK_P REFCLK_N
RX_P RX_N
002aac211
Fig 1.
Block diagram
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PX1011B
PCI Express stand-alone X1 PHY
7. Pinning information
7.1 Pinning
ball A1 index area
PX1011B-EL1/G PX1011BI-EL1/G
123456789
A B C D E F G H J
002aad017
Transparent top view
Fig 2.
Pin configuration for LFBGA81
1 A B C D E F G H J VSS REFCLK_P REFCLK_N VSS RX_P RX_N VSS TX_P TX_N
2 RXIDLE VSS VSS VSS VSS VSS VSS VSS VREFS
3 RXDATA6 RXDATA7 VDDD2 VDD VDDD1 TCK TDI TDO RESET_N
4 RXDATA4 RXDATA5 VSS VDDA2 TMS TRST_N VSS TXIDLE RXPOL
5 RXDATA3 VSS VDDD2 VDDA1 VDDD1 VDDD3 VDDD2 VSS TXCOMP
6 RXDATA1 RXDATA2 VSS PVT VDDD3 VDDD3 VSS PWRDWN0 PWRDWN1
7 RXDATAK RXDATA0 VDDD2 VSS VDDD2 VSS VDDD2 RXDET_ LOOPB TXDATAK
8 RXCLK VSS RXVALID PHYSTATUS VSS TXDATA3 TXDATA5 VSS TXCLK
9 RXSTATUS0 RXSTATUS1 RXSTATUS2 TXDATA0 TXDATA1 TXDATA2 TXDATA4 TXDATA6 TXDATA7
002aad018
Transparent top view.
Fig 3.
Ball mapping
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PX1011B
PCI Express stand-alone X1 PHY
7.2 Pin description
The PHY input and output pins are described in Table 4 to Table 11. Note that input and output is defined from the perspective of the PHY. Thus a signal on a pin described as an output is driven by the PHY and a signal on a pin described as an input is received by the PHY. A basic description of each pin is provided.
Table 4. Symbol RX_P RX_N TX_P TX_N Table 5. Symbol TXDATA[7:0] TXDATAK PCI Express serial data lines Pin E1 F1 H1 J1 Type input input output output Signaling PCIe I/O PCIe I/O PCIe I/O PCIe I/O Description differential input receive pair with 50 on-chip termination differential output transmit pair with 50 on-chip termination
PXPIPE interface transmit data signals Pin J9, H9, G8, G9, F8, F9, E9, D9 J7 Type input input Signaling SSTL_2 SSTL_2 Description 8-bit transmit data input from the MAC to the PHY selection input for the symbols of transmit data; LOW = data byte; HIGH = control byte
Table 6. Symbol
PXPIPE interface receive data signals Pin B3, A3, B4, A4, A5, B6, A6, B7 A7 Type output output Signaling SSTL_2 SSTL_2 Description 8-bit receive data output from the PHY to the MAC selection output for the symbols of receive data; LOW = data byte; HIGH = control byte
RXDATA[7:0] RXDATAK
Table 7. Symbol
PXPIPE interface command signals Pin H7 Type input Signaling SSTL_2 Description used to tell the PHY to begin a receiver detection operation or to begin loopback; LOW = reset state forces TX output to electrical idle. TXIDLE should be asserted while in power states P0s and P1. used when transmitting the compliance pattern; HIGH-level sets the running disparity to negative signals the PHY to perform a polarity inversion on the receive data; LOW = PHY does no polarity inversion; HIGH = PHY does polarity inversion PHY reset input; active LOW transceiver power-up and power-down inputs (see Table 12); 0x2 = reset state
RXDET_ LOOPB
TXIDLE
H4
input
SSTL_2
TXCOMP
J5
input
SSTL_2
RXPOL
J4
input
SSTL_2
RESET_N PWRDWN0 PWRDWN1
J3 H6 J6
input input input
SSTL_2 SSTL_2 SSTL_2
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PX1011B
PCI Express stand-alone X1 PHY
PXPIPE interface status signals Pin C8 D8 Type output output Signaling SSTL_2 SSTL_2 Description indicates symbol lock and valid data on RX_DATA and RX_DATAK used to communicate completion of several PHY functions including power management state transitions and receiver detection indicates receiver detection of an electrical idle; this is an asynchronous signal encodes receiver status and error codes for the received data stream and receiver detection (see Table 14)
Table 8. Symbol RXVALID
PHYSTATUS
RXIDLE RXSTATUS0 RXSTATUS1 RXSTATUS2 Table 9. Symbol TXCLK
A2 A9 B9 C9
output output output output
SSTL_2 SSTL_2 SSTL_2 SSTL_2
Clock and reference signals Pin J8 Type input Signaling SSTL_2 Description source synchronous 250 MHz transmit clock input from MAC. All input data and signals to the PHY are synchronized to this clock. source synchronous 250 MHz clock output for received data and status signals bound for the MAC. 100 MHz reference clock input. This is the spread spectrum source clock for PCI Express. Differential pair input with 50 on-chip termination. input or output to create a compensation signal internally that will adjust the I/O pads characteristics as PVT drifts. Connect to VDD through a 49.9 resistor. reference voltage input for SSTL_2 class I signaling. Connect to 1.25 V.
RXCLK
A8
output
SSTL_2
REFCLK_P REFCLK_N
B1 C1
input input
PCIe I/O PCIe I/O
PVT
D6
-
analog I/O
VREFS
J2
input
Table 10. Symbol TMS TRST_N TCK TDI TDO
3.3 V JTAG signals Pin E4 F4 F3 G3 H3 Type input input input input output Signaling 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS Description test mode select input test reset input for the JTAG interface; active LOW test clock input for the JTAG interface test data input test data output
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PX1011B
PCI Express stand-alone X1 PHY
PCI Express PHY power supplies Pin D5 D4 E3, E5 C3, C5, C7, E7, G5, G7 E6, F5, F6 D3 A1, B2, B5, B8, C2, C4, C6, D1, D2, D7, E2, E8, F2, F7, G1, G2, G4, G6, H2, H5, H8 Type power power power power power power ground Signaling Description 1.2 V analog power supply for serializer and de-serializer 3.3 V analog power supply for serializer and de-serializer 3.3 V power supply for JTAG I/O 2.5 V power supply for SSTL_2 I/O 1.2 V power supply for core 1.2 V power supply for high-speed serial PCI Express I/O pads and PVT ground
Table 11. Symbol VDDA1 VDDA2 VDDD1 VDDD2 VDDD3 VDD VSS
8. Functional description
The main function of the PHY is to convert digital data into electrical signals and vice versa. The PCI Express PHY handles the low level PCI Express protocol and signaling. The PX1011B PCI Express PHY consists of the Physical Coding Sub-layer (PCS), a Serializer and De-serializer (SerDes) and a set of I/Os (pads). The PCI Express PHY handles the low level PCI Express protocol and signaling. This includes features such as Clock and Data Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection. The PXPIPE interface between the MAC and PX1011B is a superset of the PHY Interface for the PCI Express (PIPE) specification. The following feature have been added:
* Source synchronous clocks for RX and TX data to simplify timing closure.
The 8-bit data width PXPIPE interface operates at 250 MHz with SSTL_2 class I signaling. PX1011B does not integrate SSTL_2 termination resistors inside the IC. The PCI Express link consists of a differential input pair and a differential output pair. The data rate of these signals is 2.5 Gbit/s.
8.1 Receiving data
Incoming data enters the chip at the RX interface. The receiver converts these signals from small amplitude differential signals into rail-to-rail digital signals. The carrier detect circuit detects whether data is present on the line and passes this information through to the SerDes and PCS. If a valid stream of data is present the Clock and Data Recovery unit (CDR) first recovers the clock from the data and then uses this clock for re-timing the data (i.e., recovering the data).
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PCI Express stand-alone X1 PHY
The de-serializer or Serial-to-Parallel converter (S2P) de-serializes this data into 10-bits parallel data. Since the S2P has no knowledge about the data, the word alignment is still random. This is fixed in the digital domain by the PCS block. It first detects a 10-bit comma character (K28.5) from the random data stream and aligns the bits. Then it converts the 10-bit raw data into 8-bit words using 8b/10b decoding. An elastic buffer and FIFO brings the resulting data to the right clock domain, which is the RX source synchronous clock domain.
8.2 Transmitting data
When the PHY transmits, it receives 8-bit data from the MAC. This data is encoded using an 8b/10b encoding algorithm. The 2 bits overhead of the 8b/10b encoding ensures the serial data will be DC-balanced and has a sufficient 0-to-1 and 1-to-0 transition density for clock recovery at the receiver side. The serializer or Parallel-to-Serial converter (P2S) serializes the 10 bits data into serial data streams. These data streams are latched into the transmitter, where they are converted into small amplitude differential signals. The transmitter has built-in de-emphasis for a larger eye opening at the receiver side. The PLL has a sufficiently high bandwidth to handle a 100 MHz reference clock with a 30 kHz to 33 kHz spread spectrum.
8.3 Clocking
There are three clock signals used by the PX1011B:
* REFCLK is a 100 MHz external reference clock that the PHY uses to generate the
250 MHz data clock and the internal bit rate clock. This clock may have 30 kHz to 33 kHz spread spectrum modulation.
* TXCLK is a reference clock that the PHY uses to clock the TXDATA and command.
This source synchronous clock is provided by the MAC. The PHY expects that the rising edge of TXCLK is centered to the data. The TXCLK has to be synchronous with RXCLK.
* RXCLK is a source synchronous clock provided by the PHY. The RXDATA and status
signals are synchronous to this clock. The PHY aligns the rising edge of RXCLK to the center of the data. RXCLK may be used by the MAC to clock its internal logic.
8.4 Reset
The PHY must be held in reset until power and REFCLK are stable. It takes the PHY 64 s maximum to stabilize its internal clocks. RXCLK frequency is the same as REFCLK frequency, 100 MHz, during this time. The PHY de-asserts PHYSTATUS when internal clocks are stable. The PIPE specification recommends that while RESET_N is asserted, the MAC should have RXDET_LOOPB de-asserted, TXIDLE asserted, TXCOMP de-asserted, RXPOL de-asserted and power state P1. The MAC can also assert a reset if it receives a physical layer reset packet.
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PX1011B
PCI Express stand-alone X1 PHY
RXCLK
RESET_N
PHYSTATUS 100 MHz 250 MHz
002aac172
Fig 4.
Reset
8.5 Power management
The power management signals allow the PHY to manage power consumption. The PHY meets all timing constraints provided in the PCI Express base specification regarding clock recovery and link training for the various power states. Four power states are defined: P0, P0s, P1 and P2. P0 state is the normal operational state for the PHY. When directed from P0 to a lower power state, the PHY can immediately take whatever power saving measures are appropriate. In states P0, P0s and P1, the PHY keeps internal clocks operational. For all state transitions between these three states, the PHY indicates successful transition into the designated power state by a single cycle assertion of PHYSTATUS. For all power state transitions, the MAC must not begin any operational sequences or further power state transitions until the PHY has indicated that the initial state transition is completed. TXIDLE should be asserted while in power states P0s and P1.
* P0 state: All internal clocks in the PHY are operational. P0 is the only state where the
PHY transmits and receives PCI Express signaling. P0 is the appropriate PHY power management state for most states in the Link Training and Status State Machine (LTSSM). Exceptions are listed for each lower power PHY state (P0s, P1 and P2).
* P0s state: The MAC will move the PHY to this state only when the transmit channel is
idle. While the PHY is in either P0 or P0s power states, if the receiver is detecting an electrical idle, the receiver portion of the PHY can take appropriate power saving measures. Note that the PHY is capable of obtaining bit and symbol lock within the PHY-specified time (N_FTS with or without common clock) upon resumption of signaling on the receive channel. This requirement only applies if the receiver had previously been bit and symbol locked while in P0 or P0s states.
* P1 state: Selected internal clocks in the PHY are turned off. The MAC will move the
PHY to this state only when both transmit and receive channels are idle. The PHY indicates a successful entry into P1 (by asserting PHYSTATUS). P1 should be used for the disabled state, all detect states, and L1.idle state of the Link Training and Status State Machine (LTSSM).
* P2 state: PHY will enter P1 instead.
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PX1011B
PCI Express stand-alone X1 PHY
Table 12. 00b 01b 10b 11b
[1] [2]
Summary of power management state Power management state P0, normal operation P0s, power saving state P1, lower power state illegal, PHY will enter P1 Transmitter on[1] idle[2] idle[2] Receiver on idle idle TX PLL on on on RXCLK on on on RX PLL/CDR on on off -
PWRDWN[1:0]
TXIDLE = 0 TXIDLE = 1
8.6 Receiver detect
When the PHY is in the P1 state, it can be instructed to perform a receiver detection operation to determine if there is a receiver at the other end of the link. Basic operation of receiver detection is that the MAC requests the PHY to do a receiver detect sequence by asserting RXDET_LOOPB. When the PHY has completed the receiver detect sequence, it drives the RXSTATUS signals to the value of 011b if a receiver is present, and to 000b if there is no receiver. Then the PHY will assert PHYSTATUS to indicate the completion of receiver detect operation. The MAC uses the rising edge of PHYSTATUS to sample the RXSTATUS signals and then de-asserts RXDET_LOOPB. A few cycles after the RXDET_LOOPB de-asserts, the PHYSTATUS is also de-asserted.
TXCLK
RXDET_LOOPB PWRDWN1, PWRDWN0
10b
RXCLK
PHYSTATUS RXSTATUS2, RXSTATUS1, RXSTATUS0
000b
011b
000b
002aac173
Fig 5.
Receiver detect - receiver present
8.7 Loopback
The PHY supports an internal loopback from the PCI Express receiver to the transmitter with the following characteristics. The PHY retransmits each 10-bit data and control symbol exactly as received, without applying scrambling or descrambling or disparity corrections, with the following rules:
* If a received 10-bit symbol is determined to be an invalid 10-bit code (i.e., no legal
translation to a control or data value possible), the PHY still retransmits the symbol exactly as it was received.
* If a SKP ordered set retransmission requires adding a SKP symbol to accommodate
timing tolerance correction, any disparity can be chosen for the SKP symbol.
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PCI Express stand-alone X1 PHY
* The PHY continues to provide the received data on the PXPIPE interface, behaving
exactly like normal data reception.
* The PHY transitions from normal transmission of data from the PXPIPE interface to
looping back the received data at a symbol boundary. The PHY begins to loopback data when the MAC asserts RXDET_LOOPB while doing normal data transmission. The PHY stops transmitting data from the PXPIPE interface, and begins to loopback received symbols. While doing loopback, the PHY continues to present received data on the PXPIPE interface. The PHY stops looping back received data when the MAC de-asserts RXDET_LOOPB. Transmission of data on the parallel interface begins immediately. The timing diagram of Figure 6 shows example timing for beginning loopback. In this example, the receiver is receiving a repeating stream of bytes, Rx-a through Rx-z. Similarly, the MAC is causing the PHY to transmit a repeating stream of bytes Tx-a through Tx-z. When the MAC asserts RXDET_LOOPB to the PHY, the PHY begins to loopback the received data to the differential TX_P and TX_N lines.
TXCLK
RXDET_LOOPB
TXDATA[7:0]
Tx-m
Tx-n
Tx-o
Tx-p
Tx-q
RXCLK
RXDATA[7:0]
Rx-c
Rx-d
Rx-e
Rx-f
Rx-g
TX_P, TX_N
Tx-m
Tx-n
Rx-e
002aac174
Fig 6.
Loopback start
The timing diagram of Figure 7 shows an example of switching from loopback mode to normal mode. As soon as the MAC detects an electrical idle ordered-set, the MAC de-asserts RXDET_LOOPB, asserts TXIDLE and changes the POWERDOWN signals to state P1.
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PCI Express stand-alone X1 PHY
RXCLK
RXDATA[7:0]
COM
IDL
Junk
TXCLK
RXDET_LOOPB
TXIDLE includes electrical idle ordered set TX_P, TX_N Looped back RX data Junk
001aac785
Fig 7.
Loopback end
8.8 Electrical idle
The PCI Express Base Specification requires that devices send an Electrical Idle ordered-set before TX goes to the electrical idle state. The timing diagram of Figure 8 shows an example of timing for entering electrical idle.
TXCLK
TXDATA[7:0]
ScZero
COM
IDL
TXDATAK
TXIDLE
TX_P, TX_N
active (ends with Electrical Idle ordered-set)
002aac175
Fig 8.
Electrical Idle
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Table 13 summarizes the function of some PXPIPE control signals.
Table 13. P0: 00b Control signals function summary RXDET_LOOPB 0 0 1 1 P0s: 01b P1: 10b X X 0 1 TXIDLE 0 1 0 1 0 1 0 1 1 Function description normal operation transmitter in idle loopback mode illegal illegal transmitter in idle illegal transmitter in idle receiver detect
PWRDWN[1:0]
8.9 Clock tolerance compensation
The PHY receiver contains an elastic buffer used to compensate for differences in frequencies between bit rates at the two ends of a link. The elastic buffer is capable of holding at least seven symbols to handle worst case differences (600 ppm) in frequency and worst case intervals between SKP ordered-sets. The PHY is responsible for inserting or removing SKP symbols in the received data stream to avoid elastic buffer overflow or underflow. The PHY monitors the receive data stream, and when a Skip ordered-set is received, the PHY can add or remove one SKP symbol from each SKP ordered-set as appropriate to manage its elastic buffer. Whenever a SKP symbol is added or removed, the PHY will signal this to the MAC using the RXSTATUS signals. These signals have a non-zero value for one clock cycle and indicate whether a SKP symbol was added or removed from the received SKP ordered-set. RXSTATUS should be asserted during the clock cycle when the COM symbol of the SKP ordered-set is moved across the parallel interface. If the removal of a SKP symbol causes no SKP symbols to be transferred across the parallel interface, then RXSTATUS is asserted at the same time that the COM symbol (that was part of the received skip ordered-set) is transmitted across the parallel interface. Figure 9 shows a sequence where the PHY inserted a SKP symbol in the data stream. Figure 10 shows a sequence where the PHY removed a SKP symbol from a SKP ordered-set.
RXCLK
RXDATA[7:0]
active
COM
SKP
SKP
active
RXVALID RXSTATUS2, RXSTATUS1, RXSTATUS0 000b 001b 000b
001aac779
Fig 9.
Clock correction - insert a SKP
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PCI Express stand-alone X1 PHY
RXCLK
RXDATA[7:0]
active
COM
SKP
active
RXVALID RXSTATUS2, RXSTATUS1, RXSTATUS0 000b 010b 000b
002aac176
Fig 10. Clock correction - remove a SKP
8.10 Error detection
The PHY is responsible for detecting receive errors of several types. These errors are signaled to the MAC layer using the receiver status signals RXSTATUS.
Table 14. Function table PXPIPE status interface signals Output pin RXSTATUS2 RXSTATUS1 RXSTATUS0 Received data OK One SKP added One SKP removed Receiver detected 8b/10b decode error Elastic buffer overflow Elastic buffer underflow Receive disparity error L L L L H H H H L L H H L L H H L H L H L H L H
Operating mode
Because of higher level error detection mechanisms (like CRC) built into the data link layer of PCI Express, there is no need to specifically identify symbols with errors. However, timing information about when the error occurred in the data stream is important. When a receive error occurs, the appropriate error code is asserted for one clock cycle at the point closest to where the error actually occurred. There are four error conditions that can be encoded on the RXSTATUS signals. If more than one error should happen to occur on a received byte, the errors are signaled with the priority shown below. 1. 8b/10b decode error 2. Elastic buffer overflow 3. Elastic buffer underflow 4. Disparity error
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PCI Express stand-alone X1 PHY
8.10.1 8b/10b decode errors
For a detected 8b/10b decode error, the PHY places an EDB (EnD Bad) symbol in the data stream in place of the bad byte, and encodes RXSTATUS with a decode error during the clock cycle when the effected byte is transferred across the parallel interface. In Figure 11 the receiver is receiving a stream of bytes Rx-a through Rx-z, and byte Rx-c has an 8b/10b decode error. In place of that byte, the PHY places an EDB on the parallel interface, and sets RXSTATUS to the 8b/10b decode error code. Note that a byte that cannot be decoded may also have bad disparity, but the 8b/10b error has precedence.
RXCLK
RXDATA[7:0]
Rx-a
Rx-b
EDB
Rx-d
Rx-e
RXVALID RXSTATUS2, RXSTATUS1, RXSTATUS0 000b 100b 000b
001aac780
Fig 11. 8b/10b decode errors
8.10.2 Disparity errors
For a detected disparity error, the PHY asserts RXSTATUS with the disparity error code during the clock cycle when the effected byte is transferred across the parallel interface. In Figure 12 the receiver detected a disparity error on Rx-c data byte, and indicates this with the assertion of RXSTATUS.
RXCLK
RXDATA[7:0]
Rx-a
Rx-b
Rx-c
Rx-d
Rx-e
RXVALID RXSTATUS2, RXSTATUS1, RXSTATUS0 000b 111b 000b
001aac781
Fig 12. Disparity errors
8.10.3 Elastic buffer
For elastic buffer errors, an underflow is signaled during the clock cycle when the spurious symbol is moved across the parallel interface. The symbol moved across the interface is the EDB symbol. In the timing diagram Figure 13, the PHY is receiving a repeating set of symbols Rx-a through Rx-z. The elastic buffer underflow causing the EDB symbol to be inserted between the Rx-c and Rx-d symbols. The PHY drives RXSTATUS to indicate buffer underflow during the clock cycle when the EDB is presented on the parallel interface.
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RXCLK
RXDATA[7:0]
Rx-a
Rx-b
Rx-c
EDB
Rx-d
RXVALID RXSTATUS2, RXSTATUS1, RXSTATUS0 000b 110b 000b
001aac782
Fig 13. Elastic buffer underflow
For an elastic buffer overflow, the overflow is signaled during the clock cycle where the dropped symbol would have appeared in the data stream. In the timing diagram of Figure 14, the PHY is receiving a repeating set of symbols Rx-a through Rx-z. The elastic buffer overflows causing the symbol Rx-d to be discarded. The PHY drives RXSTATUS to indicate buffer overflow during the clock cycle when Rx-d would have appeared on the parallel interface.
RXCLK
RXDATA[7:0]
Rx-a
Rx-b
Rx-c
Rx-e
Rx-f
RXVALID RXSTATUS2, RXSTATUS1, RXSTATUS0 000b 101b 000b
001aac783
Fig 14. Elastic buffer overflow
8.11 Polarity inversion
To support lane polarity inversion, the PHY inverts received data when RXPOL is asserted. The PHY begins data inversion within 20 symbols after RXPOL is asserted.
RXCLK
RXDATA[7:0]
D21.5
D21.5
D10.2
D10.2
RXVALID
RXPOL
001aac786
Fig 15. Polarity inversion
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8.12 Setting negative disparity
To set the running disparity to negative, the MAC asserts TXCOMP for one clock cycle that matches with the data that is to be transmitted with negative disparity.
TXCLK
TXDATA[7:0]
data
K28.5
K28.5
K28.5
K28.5
TXCOMP byte transmitted with negative disparity TX_P, TX_N valid data K28.5- K28.5+
002aac177
Fig 16. Setting negative disparity
8.13 JTAG boundary scan interface
Joint Test Action Group (JTAG) or IEEE 1149.1 is a standard, specifying how to control and monitor the pins of compliant devices on a printed-circuit board. This standard is commonly known as `JTAG Boundary Scan'. This standard defines a 5-pin serial protocol for accessing and controlling the signal levels on the pins of a digital circuit, and has some extensions for testing the internal circuitry on the chip itself, which is beyond the scope of this data sheet. Access to the JTAG interface is provided to the customer for the sole purpose of using boundary scan for interconnect test verification between other compliant devices that may reside on the board. Using JTAG for purposes other than boundary scan may produce undesired effects. The JTAG interface is a 3.3 V CMOS signaling. JTAG TRST_N must be asserted LOW for normal device operation. If JTAG is not planned to be used, it is recommended to pull down TRST_N to VSS.
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9. Limiting values
Table 15. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDD1 VDDD2 VDDD3 VDD VDDA1 VDDA2 Vesd Tstg Tj Tamb Parameter digital supply voltage 1 digital supply voltage 2 digital supply voltage 3 supply voltage analog supply voltage 1 analog supply voltage 2 electrostatic discharge voltage storage temperature junction temperature ambient temperature operating commercial industrial
[1] [2]
Conditions for JTAG I/O for SSTL_2 I/O for core for high-speed serial I/O and PVT for serializer for serializer HBM CDM
[1] [2]
Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -55 -55 0 -40
Max +4.6 +3.75 +1.7 +1.7 +1.7 +4.6 2000 500 +150 +125 +70 +85
Unit V V V V V V V V C C C C
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA. Charged Device Model: ANSI/EOS/ESD-S5.3.1-1999, standard for ESD sensitivity testing, Charged Device Model - component level; Electrostatic Discharge Association, Rome, NY, USA.
10. Thermal characteristics
Table 16. Symbol Rth(j-a) Rth(j-c)
[1]
Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions in free air in free air
[1] [1]
Typ 44 10
Unit K/W K/W
Significant variations can be expected due to system variables, such as adjacent devices, or actual air flow across the package.
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11. Characteristics
Table 17. Symbol Supplies VDDD1 VDDD2 VDDD3 VDD VDDA1 VDDA2 IDDD1 IDDD2 IDDD3 IDD IDDA1 IDDA2 Receiver UI VRX_DIFFp-p tRX_MAX_JITTER VIDLE_DET_DIFFp-p ZRX_DC ZRX_HIGH_IMP_DC RLRX_DIFF RLRX_CM tlock(CDR)(ref) tlock(CDR)(data) tRX_latency Reference clock fclk(ref) fmod(clk)(ref) fmod(clk)(ref) VIH(se)REFCLK VIL(se)REFCLK ZC-DC reference clock frequency reference clock modulation frequency range reference clock modulation frequency REFCLK single-end HIGH-level input voltage REFCLK single-end LOW-level input voltage clock source DC impedance 99.97 -0.5 30 -0.3 40 100 0.7 0 50 100.03 MHz +0 33 1.15 60 % kHz V V unit interval differential input peak-to-peak voltage maximum receiver jitter time electrical idle detect threshold DC input impedance powered-down DC input impedance differential return loss common mode return loss CDR lock time (reference loop) CDR lock time (data loop) receiver latency 1 clock cycle is 4 ns 399.88 400 0.175 65 40 200 15 6 6 50 400.12 ps 1.2 0.6 175 60 50 2.5 13 V UI mV k dB dB s s clock cycle digital supply voltage 1 digital supply voltage 2 digital supply voltage 3 supply voltage analog supply voltage 1 analog supply voltage 2 digital supply current 1 digital supply current 2 digital supply current 3 supply current analog supply current 1 analog supply current 2 for JTAG I/O for SSTL_2 I/O for core for high-speed serial I/O and PVT for serializer for serializer for JTAG I/O for SSTL_2; no load for core for high-speed serial I/O and PVT for serializer for serializer 3.0 2.3 1.15 1.15 1.15 3.0 0.1 5 15 15 7 3.3 2.5 1.2 1.2 1.2 3.3 1 24 10 20 20 10 3.6 2.7 1.3 1.3 1.3 3.6 2 35 15 28 28 15 V V V V V V mA mA mA mA mA mA PCI Express PHY characteristics Parameter Conditions Min Typ Max Unit
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Table 17. Symbol dV/dt
PCI Express PHY characteristics ...continued Parameter rate of change of voltage Conditions at rising edge; measured from -150 mV to +150 mV on the differential waveform; Figure 17 at falling edge; measured from +150 mV to -150 mV on the differential waveform; Figure 17 Min 0.6 Typ Max 4.0 Unit V/ns
0.6
-
4.0
V/ns
VIH VIL REFCLK Transmitter UI VTX_DIFFp-p tTX_EYE_m-mJITTER
differential input HIGH voltage differential input LOW voltage duty cycle on pin REFCLK on pin REFCLK_N and pin REFCLK_P
+150 40
-
-150 60
mV mV %
unit interval differential peak-to-peak output voltage maximum time between the jitter median and maximum deviation from the median maximum transmitter jitter time de-emphasized differential output voltage ratio D+/D- TX output rise time D+/D- TX output fall time RMS AC peak common mode output voltage
399.88 400 0.8 35
400.12 ps 1.2 50 V ps
tTX_JITTER_MAX VTX_DE_RATIO tTX_RISE tTX_FALL VTX_CM_ACp
-3.0 50 50 0 0 0 12 6 40 75 1 clock cycle is 4 ns 4 -
60 75 75 20 50 100 -
100 -4.0 20 100 25 3.6 90 60 200 50 9 2.5 64 64
ps dB ps ps mV mV mV V mA dB dB nF s clock cycle s s s
VCM_DC_ACT_IDLE absolute delta of DC common mode voltage during L0 and electrical idle VCM_DC_LINE VTX_CM_DC ITX_SHORT RLTX_DIFF RLTX_CM ZTX_DC CTX tlock(PLL) tTX_latency tP0s_exit_latency tP1_exit_latency tRESET-PHYSTATUS absolute delta of DC common mode voltage between D+ and D- TX DC common mode voltage TX short-circuit current limit differential return loss common mode return loss transmitter DC impedance AC coupling capacitor PLL lock time transmitter latency P0s state exit latency P1 state exit latency RESET_N HIGH to PHYSTATUS LOW time
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dV/dt at rising edge
dV/dt at falling edge
REFCLK+ minus REFCLK-
002aad694
VIH = +150 mV 0.0 V VIL = -150 mV
Fig 17. Differential measurement points Table 18. Symbol fRXCLK fTXCLK VVREFS VOH(SSTL2) VOL(SSTL2) VIH(SSTL2) VIL(SSTL2) PXPIPE characteristics Parameter RXCLK frequency TXCLK frequency voltage on pin VREFS SSTL_2 HIGH-level output voltage SSTL_2 LOW-level output voltage SSTL_2 HIGH-level input voltage SSTL_2 LOW-level input voltage AC AC AC AC see Figure 18 see Figure 18 see Figure 18 see Figure 18
[1]
Conditions
Min 249.925 249.925 1.13 500 500 1500 1500
Typ 250 250 1.25 -
Max 250.075 250.075 1.38 -
Unit MHz MHz V V V
VTT + 0.61 Vref + 0.31 -
VTT - 0.61 V Vref - 0.31 V ps ps ps ps
Input signals; measured with respect to TXCLK tsu(TX)(PXPIPE) set-up time of PXPIPE input signal th(TX)(PXPIPE) hold time of PXPIPE input signal Output signals; measured with respect to RXCLK tsu(RX)(PXPIPE) set-up time of PXPIPE output signal th(RX)(PXPIPE)
[1]
hold time of PXPIPE output signal
Reference voltage for SSTL_2 class I I/O.
TXCLK
PXPIPE INPUT t su(TX)(PXPIPE) t h(TX)(PXPIPE)
RXCLK
PXPIPE OUTPUT t su(RX)(PXPIPE) t h(RX)(PXPIPE)
002aac316
Fig 18. Definition of PXPIPE timing
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001aac789
0.6 0.5 differential signal 0.4 (V) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 unit intervals 1.2
Tamb = 25 C; nominal VDD
Fig 19. Transition eye
001aac790
0.6 0.5 differential signal 0.4 (V) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 unit intervals 1.2
Tamb = 25 C; nominal VDD
Fig 20. Non transition eye
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12. Package outline
LFBGA81: plastic low profile fine-pitch ball grid array package; 81 balls; body 9 x 9 x 1.05 mm SOT643-1
D
B
A
ball A1 index area
A E
A2
A1
detail X
e1 e b
v M C A B w M C
C y1 C y
J H G F E D C B A ball A1 index area e2 e
1
2
3
4
5
6
7
8
9
X 5 scale 10 mm
0
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.4 0.3 A2 1.20 0.95 b 0.5 0.4 D 9.1 8.9 E 9.1 8.9 e 0.8 e1 6.4 e2 6.4 v 0.15 w 0.08 y 0.12 y1 0.1
OUTLINE VERSION SOT643-1
REFERENCES IEC JEDEC MO-205 JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 00-11-01 02-03-28
Fig 21. Package outline SOT643-1 (LFBGA81)
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13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 22) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 19 and 20
Table 19. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 20. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 22.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 22. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 21. Acronym BER BIST CMOS CRC EMI ESD FPGA LTSSM MAC P2S PCI PCS PHY PLL PIPE PVT S2P Abbreviations Description Bit Error Rate Built-In Self Test Complementary Metal Oxide Semiconductor Cyclic Redundancy Check ElectroMagnetic Interference ElectroStatic Discharge Field Programmable Gate Array Link Training and Status State Machine Media Access Control Parallel to Serial Peripheral Component Interconnect Physical Coding Sub-layer PHYsical layer Phase-Locked Loop PHY Interface for the PCI Express Process Voltage Temperature Serial to Parallel
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Abbreviations ...continued Description Serializer and De-serializer SKiP Stub Series Terminated Logic for 2.5 Volts
Table 21. Acronym SerDes SKP SSTL_2
15. References
[1] [2] PCI Express Base Specification -- Rev. 1.0a - PCISIG PHY Interface for the PCI Express Architecture (PIPE) Specification Version 1.00 -- Intel Corporation
16. Revision history
Table 22. Revision history Release date 20080319 Data sheet status Product data sheet Change notice Supersedes PX1011B_1 Document ID PX1011B_2 Modifications:
*
Table 17 "PCI Express PHY characteristics": - sub-section "Supplies", symbol IDDD2: Min value changed from "10 mA" to "-" - sub-section "Supplies", symbol IDDD2: Typ value changed from "18 mA" to "24 mA" - sub-section "Supplies", symbol IDDD2: Max value changed from "25 mA" to "35 mA" - sub-section "Supplies", symbol IDD: Max value changed from "25 mA" to "28 mA" - sub-section "Supplies", symbol IDDA1: Max value changed from "25 mA" to "28 mA" - added sub-section header row "Reference clock" - symbol VIH(se)REFCLK: Max value changed from "-" to "1.15 V" - symbol VIL(se)REFCLK: Min value changed from "-" to "-0.3 V" - sub-section "Reference clock": added symbol/parameter "ZC-DC", "dV/dt", "VIH", "VIL", "REFCLK" - sub-section "Transmitter", symbol tTX_RISE: Min value changed from "60 ps" to "50 ps" - sub-section "Transmitter", symbol tTX_RISE: Typ value changed from "70 ps" to "75 ps" - sub-section "Transmitter", symbol tTX_RISE: Max value changed from "80 ps" to "-" - sub-section "Transmitter", symbol tTX_FALL: Min value changed from "60 ps" to "50 ps" - sub-section "Transmitter", symbol tTX_FALL: Typ value changed from "70 ps" to "75 ps" - sub-section "Transmitter", symbol tTX_FALL: Max value changed from "80 ps" to "-"
* *
PX1011B_1
Added (new) Figure 17 "Differential measurement points" Section 17.3 "Disclaimers": added "Quick reference data" disclaimer Objective data sheet -
20080213
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17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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PCI Express stand-alone X1 PHY
19. Contents
1 2 2.1 2.2 2.3 2.4 2.5 2.6 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.10.1 8.10.2 8.10.3 8.11 8.12 8.13 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PCI Express interface . . . . . . . . . . . . . . . . . . . . 1 PHY/MAC interface. . . . . . . . . . . . . . . . . . . . . . 1 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . 2 Power management . . . . . . . . . . . . . . . . . . . . . 2 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 8 Receiving data . . . . . . . . . . . . . . . . . . . . . . . . . 8 Transmitting data . . . . . . . . . . . . . . . . . . . . . . . 9 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power management . . . . . . . . . . . . . . . . . . . . 10 Receiver detect. . . . . . . . . . . . . . . . . . . . . . . . 11 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical idle . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock tolerance compensation . . . . . . . . . . . . 14 Error detection . . . . . . . . . . . . . . . . . . . . . . . . 15 8b/10b decode errors . . . . . . . . . . . . . . . . . . . 16 Disparity errors . . . . . . . . . . . . . . . . . . . . . . . . 16 Elastic buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Polarity inversion. . . . . . . . . . . . . . . . . . . . . . . 17 Setting negative disparity . . . . . . . . . . . . . . . . 18 JTAG boundary scan interface . . . . . . . . . . . . 18 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19 Thermal characteristics. . . . . . . . . . . . . . . . . . 19 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 24 Soldering of SMD packages . . . . . . . . . . . . . . 25 Introduction to soldering . . . . . . . . . . . . . . . . . 25 Wave and reflow soldering . . . . . . . . . . . . . . . 25 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 26 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 28 Legal information. . . . . . . . . . . . . . . . . . . . . . . 29 17.1 17.2 17.3 17.4 18 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 29 29 29 29 30
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 March 2008 Document identifier: PX1011B_2

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